Pulse discriminating and control circuit for multivibrator circuits



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2 Sheets--Sheetl 1 Filed June l2, 1959 INVENTOR l ATTORNEYS July 3, 1962 A. JOHNSON 3,042,813

C. PULSE DISCRIMINATING AND CONTROL CIRCUIT FOR MULTIVIBRATOR CIRCUITS Filed June l2, 1959 2 Sheets-Sheet 2 WAL/E FORMS OF PRIOR ART COUNTERS CARL A. JOHNSON iBS-:VUUIIUIHIUII'LHIIILI'U'LI'ULI'L PULsEs 984 00 2 90" STAGE (.02 2. Haz.

l 98.1 2s 96 '04 STAGE wAvEFoRMs oF A COUNTER uslNG lNvENTloN A couNT SEIJII'IDILHNLI'UUUUUUUUM PULSES I l l 2 am STAGE aan L98' 2. r 3. Ql l I I l L l 1 STAGE l 22 um STAGE I' 2s am STAGE J CARRY ovER l 0 I 7G- mgl) 2S los O6 couNT Pu SES FIG 4 INVENTOR ATTORNEYS United States Patent O ware Filed .inne 12, 1959, Ser. No. 819,945 Claims. (Cl. 307-885) 'I'his invention relates generally to multivibrator circuits, and more particularly to circuitry for improving the reliability of such circuits, especially transistorized iiip-ops.

The ever expanding utilization and the increased complexity of electronic equipment has led to a `determined effort to replace thermionic tubes with components such as transistors to take advantage of their low power consumption, small heat dissipation, miniature size, and lesser likelihood of failure. Recently the greater portion of research on transistors and transistor circuits has been concentrated on the junction type of transistors including surface barrier, diused junction among other types of junction transistors. Transistors of the junction type are classed into two basic conductivity types. The n-p-n transistor comprises a body of semi-conductive material such as germanium or silicon containing a thin layer of p-type material interposed between Zones of n-type material. In the p-n-p transistor, the reverse is true. Ohmic nonrectifying connections are made to each zone with a base connection made to the intermediate zone and emitter and collector connections made respectively to the outer zones.

A basic component of electronic data handling systems. is the ilip-flop circuit or bistable multivibrator which can be switched alternately betweenl its two conditions of stable equilibrium by means of trigger pulses. If the switching is accomplished by pulses arriving from a single trigger input, the ip-ilop becomes a scale-of-two or radix two counterstage and as such is usable as a basic building block in electronic data handling equipment as part of a binaryfcoded decade counter, accumulator, or the like.

Much eifort has been placed in attempting to provide a ransistor flip-flop circuit which can be reliably triggered at relatively high repetitive rates by input trigger pulses on a single input line. Generally the objection in such circuits is that the circuit becomes sensitive to pulse width variations, especially in pulses that have become widened after being repeatedly amplified without inter-g mediate pulse forming. If the pulse is too wide both transistors in the flip-flop may become atlbest partially conductive during the pulse, and the Hip-flop is likely to come to rest in either one of its two stable states regardless of what state it was in prior to the application of the input trigger.

Another recurrent problem in electronic data handling systems'is the presence of a substandard or runt pulse (commonly referred to as a zero or noise signal) causing a ilip-tlop to switch states thereby giving a false indication that a valid pulse was received.

-According to this invention a iiip-op circuit may be reliably switched from one stable state to the second stable state by a single electrical impulse on a common input line. The circuitiis made relatively independent of pulse width variations and insensitive to undesirable runt pulses, thus eliminating the need for many pulse forming networks in data handling machines.

Accordingly it is an object of this invention to provide an improved `transistorized bistable counting circuit.

It is another object of this invention to provide an improved bistable counting stage which is completely relatively insensitive to increases in pulse widths.

It is still a further object of this invention to provide an improved bistable counting stage which is nonresponsive to runt pulses.

It is still another object of this invention to provide a counting stage which `does not switch stable states until cessation of the input trigger.

It is yet another object of this invention to provide ka counting stage which discriminates between pulses of high and low voltage-time integrals.

It is still another object of this invention to provide an electronic counter which advances the count upon cessation of the pulses to be counted.

Other objects and advantages of this invention will become apparent to those skilled in the art from a detailed reading of the specification and drawings wherein:

FIGURE l is a circuit schematic of theinvention.

FiGURE 2 is a sketch of waveforms associated with a typical electronic counter.

FIGURE 3 is a sketch of waveforms associated with a counter consisting of stages madefin accordance to the teachings of this invention.

FIGURE 4 is a block diagram of a counter utilizing counting stages of this invention.

A transistorized bistable multivibrator, or flip-flop as it is sometimes termed, is shown in box 10 of FIGURE l in conjunction with two transistors 11 and 13 connected as emitter followers, and it all operates in the usual manner. In the embodiment of the flip-ilop illustrated, with the component values as shown, the output voltages provided to the utilization circuits l2 and 14 are nominally -2 and O (ground) volts; thus being compatible, asis generally preferable, with direct-coupled transistorized logic. A description of direct-coupled transistorized logic is given by Beter, Bradley and Brown in Surface- Barrier Transistor Switching Circuits, IRE Convention Record, par-t 4, pages 139 if., New York, 1955.

In the following discussion the term negative or relatively low voltage refers to the -2 volts; while the term positive or relatively high voltage refers to 0 volts. By arbitrary definition herein as to any given output line, a relatively hig voltage thereonisindicative of a predetermined condition or state, while afrelatively low voltage thereon is indicative of the absence of such a condition or state. As an example, a relatively high voltage on line 16 is indicative that flipftlop lil is in a.0 state, while a relatively low voltage on line 16 indicates a l state for iiip-ilop i6. The converse is true for output line 22; that is, a relatively high vol-tage thereon indicates a l state for the flip-flop while a relatively low voltage thereonindicates a 0 state. therefor. To change the tlip-opfrom a-O state to a l state, an input signal may be applied over line. 20, while an input signal on line 1S may revert the flip-flop -back to its v0 state.

To convert Hip-flop 10 into a countingcircuit, diode AND gates 24 and 26. may be coupled together, to-receive trigger pulses at terminal 2S, and respectively between an input and output of flip-op l0. Each time a positive pulse is applied to terminal 28, flip-flop 10 should change state. The left AND gate 26 is coupled to the l input line 20, and the right AND .gate24 is coupled to the 0 input line 1'8. The 0 output line 16 is coupled to one input of the left gate 26, while the l output line 22 is coupledto one input of the right gate 24, and the initial trigger input signal terminal 28 is coupled to the other inputs of both gates 24 and 26. 'Ihese gates or AND circuits are preferably typical logical diode nets. In such a circuit, for example in circuit 24, the inputs thereto are applied to the .cathodeends of sistance 40. When the ip-op output line 22 is relatively high in Voltage, junction 38 moves up and down `in voltage in correspondence with the voltage excursions of a trigger signal at terminal 28. However, when output line 22 is relatively low in voltage, junction 38 stays at a relatively low voltage regardless of what occurs at terminal 28. The junction 38 voltage is always relatively low unless both inputs to the cathode ends of diodes 34 and 36 are relatively high. This provides a logical AND tunction'indication at junction 38. It may also be said that circuit 24 gates a trigger signal in accordance with the state of ip-op 10. Y

Y If flip-flop 10 is in the l state, i.e., if there is a relatively high voltage on line 22, and if at the same time a positive-going trigger pulse 42 is applied to terminal 28, gate 24 provides a positive or relatively high voltage at junction L38, while gate 26 maintains a relatively low voltage at junction 44. When the positive voltage at junction 38 is coupled to line 18, flip-flop 10 switches from the l state to the state. Similarly, when line 16 has a relatively high voltage thereon, gate 26 gates a trigger pulse from terminal 28l and the resulting relatively high voltage at junction 44 is coupled to input line 20 to switch nip-flop to the fl state. Thus it is Vseen that flip-hop V10 may switch stateY each time a trigger pulse is applied to the single input terminal 28 regardless of the state of the hip-flop and thus provides a modulo two counter. Y

The circuitry so far described in detail is conventional and in many situations is not as reliable as'desired in that Vthe ip-flop will change state even if there is received at terminal 28 a substandard signal, such as a noise signal, zero signal, or the like and particularly any such signal as does not exist for at least a minimum time. Further, if the trigger signal exists for a time beyond that required to change the state ofthe flip-flop, it becomes questionable as to in which state the ip-op will come to rest. In other words, the circuitry so far described in detail is undesirably sensitive to substandard pulses and unreliably dependent on pulse width variations. To overcome these objections, circuits 30 and 32 are added tc cause the circuitry of FIGURE 1 to become Vdiscriminating as tothe pulses which can switch the flip-flop 'and to give a voltage-time integral range (or pulse width range with constant level voltage) possibility for such pulses so pulse Width variations within such range are immaterial.

Circuits 30 and 32 are identical and provide discrimination as to the voltage-time integral of pulses appearing on terminal 28 as well as providing a pulse on either line 18 or 20 only after cessation of the input pulse on termi- `nal 28. Without an input pulse on terminal 28, both transistors 46 and 48 are in a low impedance or conductive statekeeping their collector and base voltages essentially at ground reference potential which is the voltage on their respective emitter electrodes.

Upon a positive input to the cathode end of diode 36 of AND circuit 24 when Hip-flop 10 is in the 1 state (line 22 positive), the voltage at junction 38 changes from 2 volts to 0. volts. This positive two volt change is transferred to base electrode 50 through limiting resistance 52 and capacitor 54. This'two volts on base 50 makes the base electrode voltage positive with respect to the emitter 56 voltage, thereby reversebiasing theemitter-.base junction 58 of transistor 46 to make it non-conductive. Transistor 46 switching to a high impedance state/tends to cause a -2 volt transient on line 60 as limited by the 7 -2 volt supply through-clamp diode 62 which maintains the voltage on line 6G no less negative than -2 volts. This negative transient is passed by capacitor 674 to line 1.8 and thus to the base electrode 66V of transistor 68. Since transistor 68 already is in a low impedance or con- VVpositive voltage source, such as volts, through reductive state as indicated by the positive voltage on line 22, and additional negative voltage on the base electrode 66 will only tend to make transistor 68 more conductive and will not switch the state of the flip-flop 10.

A small constant current provided from a -20 volt supply through resistance 70 linearly charges capacitor 64 to 2 volts, the polarity thereof being as indicated in FIGURE 1. The charging time constant related to capacitor 64 is basically determined by the values of resistance 70, capacitor 64, and the magnitude of the voltage supplying the constant current, in conjunction with transistor 46, and for the values indicated in FIGURE 1 is about 2.2 microseconds. Thus to charge capacitor 64 to a full two volt charge requires about 0.22 microsecond. This time represents the narrowest y2 volt trigger pulse which is reliably acceptable at terminal 28 by the illustrated embodiment of this invention when using a -20 volt supply through a 22K'resstor (resistance 70) to charge a mit. capacitor 64 to a 2 volt charge, no limitation to such values being intended. Since transistor 68 is in a low impedance state,fthe impedance to ground from line 18 is negligible with respect to the impedance of charging resistor 70, and` since the 2 volt charge is 0.1 of the supply voltage of 20 volts, the charging is substantially linear with respect to time.

In the embodiment of FIGURE 1, the input pulse from AND circuit 24 is A.C. coupled to transistor 46 by capacitor 54, the value of which in conjunction with the value mainly of resistance 72 determines the time constant associated with the input circuit off transistor 46. Since the signal amplitudes are 2 volts, the time Afor capacitor 54 to charge after au input transient, is 4.7 microseconds if one neglects the negligible leakage current of transistor 46. Thus, following the leading edge of pulse 42, capacitor 54 is capable of maintaining transistor 46 in a high impedance (non-conductive) state for `4.7 microseconds and will do so if trigger pulse 42VlastsV that long. Transistor 46 reverts to its low impedance (conductive) state at the time trigger pulse 42 ends if it lasts less than 4.7 microseconds, or at the end of 4.7 microseconds if the trigger pulse endures that long or longer. Therefore, upon receipt at terminal 28 of any trigger pulse which exists for at least 0.22 microsecond, ip-op 10 switches (in the manner below described) to its 0 state at least at the end of V4.7 microseconds and'earlier if the trigger pulse ends earlier.

To prevent triggering back to the l state, if such is desired, the trigger pulse should cease before 4.92 (4.7-i-0.22) microseconds assuming the time constant associated with capacitor 73 is the same as capacitor 64, 0.22 microsecond in keeping with the example. Further, if it is desi-red to trigger the ip-ilop twice, hut not thrice, the trigger pulse should have a duration between 4.92 microseconds and 9.62 (4.7+4.7-|0.22) microseconds assuming the time constant associated with capacitor 77 is 4.7 microsecondsas assumed for capacitor 54 (the 0.22 microsecond -in the summation being the extra time which would be required for a third switching, i.e., back to the l state). Thus, the Vminimum and maximum pulse widths for single and double switchings, along with the minimum pulse width lfor triple switching, are defined, with it having been tacitly assumed that switching from one state to another is intsantaneous. `Although it has been indicated that the corresponding time constants in circuits 30 and 32 are the same, it is to be understood that such is not an essential and can be diierent if `desired to cause diflferent minimum pulse widths to be required to switch to one state than the other, and/ or to obtain different width output pulses to circuits 12 and 14 especially when a relat cuit, -jthe sensitivity to maximum pulse width can be removed, thereby allowing the trigger pulse to exist longer aoaaeis than 4.92 microseconds without causing double switching, since the non-conductive hold time for transistor 46 would then be equal to the trigger pulse width at all times. Under such conditions, the value of resistor 52 should be increased (for example, to 2.7K ohms) to insure conduction of transistor 46 during the absence of a trigger pulse. The same can be done for the input circuit of transistor 4S if desired.

Upon cessation of positive trigger pulse 42, the voltage `at junction 38 changes suddenly to a negative value providing a -2 volt transient to base 50 through capacitor 54. The transient causes transistor 46 to resume a low impedance (conductive) state in which it is then held Eby the volt supply through resistor 72 providing a current path for the emitter-base current of transistor 46.

Upon transistor 46 assuming a low impedance (conductive) state the voltage on line 60 suddenly changes from about -2 Volts to near ground potential causing a positive 2 volt transient. Since the collector-to-emitter impedance of transistor 46 when conductive is quite small (of the order of l ohm) capacitor 64 discharges very rapidly causing on line 18 a positive two volt transient which neutralizes the eective forward bias charge across the base-emitter junction of transistor 68. rthe input signal on line 18 is thus always a standard pulse (i.e., always the same size) regardless of pulse variations on terminal 28 as long as the trigger pulses endure at their 2 volt `.amplitude for at least the minimum time (0.22 microsecond in the example). The positive transient or input signal on line 13 makes the base 66 potential positive with respect to the emitter 74 potential which reverse ybiases the emitter-base junction of transistor 6s. As is well known, transistor 63 then begins assuming la high impedance (non-conductive) state to initiate the switching of flip-hop 10 in the usual manner.

The voltage-time integral discriminating capabilities or" circuit 32, for example, comes about Ias follows. During the non-conducting duration of transistor 46, i.e., during the existence of trigger pulse 42, capacitor 64 is allowed to charge up to -2 volts (line 60 is then at approximately 2.3 volts while line 66 is at approximately 0.3 volt), thereby basically generating the input signal for transistor 63, but of the wrong polarity. Upon cessation of trigger pulse 42, line 6h -is clamped to ground through transistor 46 rather than to -2 volts through diode 62. This switching of line 60 allows capacitor 64V to discharge through the base-emitter circuit of transistor 68 in such a polarity that the previously injected carriers (forward bias) are cancelled and transistor 68 assumes a non-conducting state. If capacitor 64 had only been partially charged, i.e., if trigger pulse 42 were narrow, to a point less than the effective charge of the excess injected carriers, transistor 68 would not have assumed the cut-oli state, and the ipJflop would not change state. Since the changing of state of the hip-flop is dependent on developing a minimum accumulated charge on capacitor 64 during the trigger pulse time, and the charge is approximately linearly dependent on the charging duration and the charging duration is apprordrnately equal to the trigger pulse width, it follows that the changing of state of the flip-flop is dependent upon the minimum trigger pulse width. With direct coupled logic, the signals are clamped either to ground or another voltage level, in this case to 2 volts, which results in constant voltage amplitude signals. It follows then that the lijp-hop with its added circuits 30, 32 is voltage-time integral discriminating, with the minimum pulse width acceptable being determined in reality not only iby the values of capacitor 64, registor 70, and their supply voltage, but also by the effective rb of transistor 68, the values of resistors 67 and 69, and the etective stored charge in the base-emitter junction of transistor 68 due to excess injected carriers.

Circuits and 32 `are also voltage-time integral discriminating in the sense above stated relative to the maxto give a false count.

6.. imum size trigger pulse usable at terminal 28, for single switching for example. That is, since pulse 42 is of constant voltage and since that pulse may be of no greater width than the sum of the times related to the time constants associated with condensers 54 and 73 (or 77 and 64) and the supply voltage (-20 volts), without the flipflop being switched twice, discrimination as to the maximum usable voltage-time integral of trigger pulse results.

Thus there is shown a bistable counting circuit which provides pulse width discrimination and initiation of the switching action of the bistable circuit with a standard pulse aiter cessation of the trigger pulse.

ri'he advantage or" utilizing this invention in counting circuits and the like will now be described with reference to the idealized waveforms in FIGURES 2 and 3. It is well known that the switching action of prior ant iptlops are initiated immediately upon presentation of a trigger pulse to the grid of a thermionic tube or base of a transistor. Such switching action is represented in the waveforms of FIGURE 2 which shows voltage indications for four binary counter stages, 2D through 23 inclusive. Count pulses S5 cause a counter, such as logically illustrated in FIGURE 4 (i.e., circuits 76-82 are only conventional fiip-ilops rather than with the addition of circuits Stl and 32 of FIGURE l), to advance count. The type of counter logically illustrated in FIGURE 4 is well known to those skilled in the art as being the type which eliminates the serial carry or borrow from the counter by providing AND circuits, such as the diode AND circuits described in FIGURE l, having inputs all lower order digit positions to provide an input trigger pulse to a given digit position. Thus for an input trigger to be provided to flip-flop 76, flip-flops 78, and 82 must all be in the l state and a count pulse on line S6 must be provided to satisfy the logicrequirexnents of AND circuit 84. The progression of the count occurs in the usual manner,

in FIGURE 2 coun-t pulses 38 periodically are applied to line 36 of FIGURE 4 to alternate respectively the states or flip-Hop 82 as indicated by voltage wave @0. The more significant digit positions alternate states as indicated by waves G2, 94 and 96. At the time denoted by dash line SiS, which time corresponds to the occurrence time of a leading edge of one of count pulses 83 in FIGURE 2, waves 9@ and 92 change from a positive voltage while wave 94 changes to ya positive voltage. It -is well known that in changingvoltage levels the change does not occur instantaneously, rather there is usually some delay in Ithe change such as caused by current saturation and high impedance eiects. Thus the change in voltage waves and 92 may be delayed as indicated by dotted lines lili) and 162, respectively.

Upon applying the waves of FIGURE 2 to the counter of FIGURE 4 when circuits 76-82 are conventional, and then especially considering the input signals to AND circuit 84, it is seen that with waves 90 and 92 being delayed in changing to a negative voltage while wave 94 is at a positive voltage, AND circuit 84 may be sufficiently satisfied to pass at least a runt or substandard pulse to ipop 76, thereby causing flip-flop 76 to prematurely change state,-which would move leading edge 104 to dash line 98, Thus the counting is sensitive to switching and signal transmission times of the various bistable elements comprising the counter.

The voltage waves illustrated in FIGURE 3 are idealized Waves taken from a counter having the logic of the counter illustrated in FIGURE 4, but utilizing bistable counting elements built according to the teaching of this invention. Count pulses SS are again applied to line 86 to advance the counter. Circuits 76, 7S, 80 and 82 each now are comprised of the circuitry shown in FIGURE 1 including hip-iop 10, circuits 30 and 32, and AND gates 24 and 26, along with the emitter followers il and 13 it desired. Input terminal 2S of FIGURE 1 is in each of the -trigger input lines il of FIGURE 4. In FIGURE 3,

time marker 98 indicates when voltage waves 9%" and 92' change form positive to negative indication and wave 54 changes from negative to positive indication. Because none of the bistable counting circuits 7e-82 when con-V structed in `accordance with FIGURE l, will ever begin to change state until cessation of the existing count pulse, there `can be no premature change in the disa-blement status ofY AND circuit 34 (or of the other AND circuits of the counter) as described .for the waves of FIGURE 2. Switching action of al1 the bistable counting elements occurs simultaneously but after cessation of la trigger pulse c3. Therefore, even if there is a slight delay in the switchin action, this delay occurs during the absence of a count pulse preventing AND circuit Se, or the others, trom being satisiied. Thus the possibility of obtaining a false count is greatly reduced if not nulliiied.

It is obvious to those skilled in the art that various types of transistors may be `substituted for the PNPS shown in the embodiment of FIGURE l, and that the polarity of all signals would be reversed for similar circuit operation when using complementary transistors.

Thus it is apparent that there is provided by this invention systems in which the various objects and advantages herein set forth are successfully achieved.

Modifications of this invention not described herein will become apparent to those of ordinary skill in the art after reading this disclosure. Therefore, it is intended that the matter containedin the foregoing description and the accompanying drawings be interpreted as illustrative and not limitative, the scope of the invention being dened in the appended claims.

What is claimed is:

l. In a multivibrator circuit having at least one input Y and at least one output at which there may be exhibited two discrete conditions at least one of which is in response to an input signal only-when the input signal has at least a predetermined amplitude, the improvement comprising a condenser coupled to said input7 means releaseably clamping said condenser to a predetermined potential, means for releasing the elect of the clamping means for at least a predetermined time, means for charging said condenser when said clamping means is released, the charge on said condenser as so developed being of such polarity as to be ineffective to cause said multivibrator circuit to change from the other of said two conditions to said one condition, the reclamping Vby said clamping Vmeans being effective to discharge ksaid condenser and cause an input signal which will so change the condition of said multivibrator if said' clamping means was released for a time suicient to allow the change on said condenser to build up to a point sutlicient to cause an input signal of a-t least said predetermined amplitude.

2. In a circuit having at least one control element which may be triggered by an input signal only if the input signal has at least a predetermined amplitude, theimprovement comprising storage means changeable at least between two predetermined conditions only if a given length of time elapses, said storage means being normally in a given one of said conditions and then incapable of supply-I ing said input signal but when in its other predetermined condition being capable of supplying an input signal of said predetermined amplitude, and means operatively responsive (1) to the leading edge of a trigger signal for changing said storage means from said one condition to its said other condition only when allowed to operate for said given time, and (2) to at least the trailing edge of said trigger signal for changing said storage means back to Said one condition to effect from the storage means an input signal the amplitude of which is then at least said predetermined amplitude only if the trigger signal has existed for said given length of time so as to allow the storage means to change to its said other condition.

3. In a circuit having at least one control element which may be triggered by an input signal only when it has at least a predetermined amplitude, the improvement comprising a condenser coupled to` said control element, means for charging said condenser, means for discharging said condenser, and means operative in response to a trigger signal for causing said charging and Vdischarging means to operate sequentially, one of lSaid charging and discharging means being normally operative while the other is normally inoperative, the leading edge of said trigger signal being effective to reverse the normal operation of each of said charging and discharging means and at least the trailing edge of said trigger signal being eective to revert the operating conditions of the charging and discharging means back to normal, the' arrangement being such that the charge on said condenser at the time of the reverting is sufficient to cause an input signal having at least said predeterminedV amplitude only if said trigger signal has existed for at least a predetermined time.

4. ln a circuit having at least one control element which may be triggered by an input signal only if the input signal has at least a predetermined amplitude and a given polarity, the improvement comprising storage means gradually changeable at least from a first predetermined limited condition to a second predetermined limited condition only if a given length of time elapses. said storage means being normally in said iirst condition and at that time incapable of supplying an input signal of said given polarity b ut when in its second condition being capable of supplying an input signal of said predetermined amplitude and given polarity, means operatively responsive (l) to the leading edge of a trigger signal for causing said storage means to start gradually changing from its rst condition toward its second condition, and (2) to at least the trailing edge of said trigger signal for causing the storage means to start changing back to said first condition to effect from the storage means an input signal havingsaid given polarity and an amplitude which, at least up to said predetermined amplitude, is dependent upon the length of timesaid trigger signal exists, the arrangement being such thatsaid input signal has said predetermined amplitude only if the trigger signal exists for said given length ottime. Y

5. For use with a utilization circuit which may be triggered only by an input signal which has at least a predetermined amplitude, the improvement comprising means responsive to a trigger signal for'causing said input signal and allowing the input signal to attain said predetermined amplitude and substantially no moreor less as long as the trigger signal when beginning at time't lasts to at least time t1 and even though the trigger signal endures to time t2 or longer, where times t0, t1, and t2 are respectively later occurring, said means including: means for generating and gradually changing said input signal to an amplitude limit of said predeterminedV amplitude in substantially no less time than (I1-t0), means responsive to the trigger signal at time t0 for starting said generating means, and a timing circuit operative from time t0 in response to, and only during the existence of, said trigger signal for causing the generation of said input signal to Stop at time t2 or `earlier if the trigger signal ends earlier but not later if the 60 Ytrigger signal ends later.

6. For use with a utilization circuit which has two control elements for respectively receiving iirst and second input signals for triggering said circuit alternately between two stable states only if the input signals have at least a predetermined amplitude, the improvement comprising first means for generating said iirst input signal, second means for generating said second input signal, two means respectively associated with said first and second generating means and respectively responsive to the leading edge of a trigger signal received thereby for starting the associated generating means and to at least the trailing edge of a trigger signal received thereby for stopping the associated generating means, and Vmeans for changing the am= g. rangement being such that said utilization circuit may be continuously triggered between its two states by successively received trigger signals which exist for at least said predetermined time.

7. The improvement as in claim 6 and further including means for initially receiving said trigger signals and for gating them to one or the other of said two means in accordance with the state of said utilization circuit.

8. An electronic circuit comprising a bistable multivibrator having two inputs for respectively receiving lirst and second input signals for triggering the multivibrator alternately between its two stable states only if the received input signals have at least a predetermined amplitude, first and second storage means respectively coupled to said inputs, each of said storage means being changeable at least from a iirst predetermined condition to a second predetermined condition only if a given length of time elapses from the receipt of a rst change-condition signal, each of said storage means being normally in said first condition and at that time incapable of supplying said input signal butwhen in its second condition 'being-capable of" supplying an' input' signal of said predetermined amplitude, and twoY means respectively for said storage means and respectively responsive to the yleading edge ofY a trigger' signal received thereby for providing said iirst change-condition signal to its respective storage means, and operatively responsive at least to the trailing edge of a trigger signal received thereby for providing a second change-condition signal which causes the respective storage means to change back to said iirst condition and to eliect from the storage means an input signal the amplitude of which is then said predetermined amplitude only if the trigger signal has existed for said given length of time.

9. A circuit as in claim 8 and further including means for initially receiving a trigger signal and gating it to one or the other of said two means in accordance with the state of said multivibrator.

10. An electric circuit comprising a bistable multivibrator having two inputs for respectively receiving rst and second input signals for triggering the multivibrator alternately between its two stable states only if the Ieceived input signals have at least a predetermined amplitude, iirst means for gradually generating and storing said tirst input signal, second means lforgradually generating and storing said second input signal, iirst switch means normally operative to keep said first means inoperative but responsive to the Ileading edge of a received trigger signal for causing the said lirst means to begin generating and storing said rst input signal, said rst switch means being also responsive at least to the trailing edge of a received trigger signal for stopping the generation of said first signal and causing the generated iirst input signal as stored to -be delivered to the associated multivibrator input, whereby said multivibrator changes state only if the trig er signal as received by said first switch means has existed for a time sufficient to allow said rst means to gradually increase the amplitude of said rst input signal to said rst predetermined amplitude, second switch means normally operative to maintain the second generating -and storing means inoperative but responsive to the leading edge of a received trigger signal for making said second means operative, the second switch means being also responsive to at least the trailing edge of a received trigger signal for stopping the generation of said second input signal and causing it to 'be delivered to the other multivibrator input whereby the multivibrator changes states only if the trigger signal as received by said second switch means existed for a time sufficient to allow the said second means to gradually generate and store an input signal which has at least said predetermined amplitude.

11. A circuit as in claim l() and further including means .for limiting the amplitude of each of said input signals to said predetermined amplitude.

12. A circuit as in claim 1l and further including two timing circuits, one for each of said switch means, for stopping the'generation of signals a predetermined time after it has reached` said predetermined amplitude if the trigger signal received by the associated switch means endures beyond said predetermined time.

13. A circuit as in claim l0 and further including means for initially receiving a trigger signal and gating it to one or the other' of said switch means in accordance with the existing state of said multivibrator.

14. A circuit as in claim 10 and further including means for initially receiving a trigger signal and gating it to one or the other of said switch means in accordance rwith the existing state of said multivibrator, said gating means being coupled to each `of the switch means by respective timing circuits the time constants of which are greater than the -time which it takes the respective generating means to generate its input signal to said predetermined amplitude.

15. A circuit as in claim 14 and further including means for limiting each of the input signals in amplitude to said predetermined amplitude.

16. A circuit as in claim l0 wherein each of the generating and storing means includes a condenser and means for charging the condenser.

17. An electronic circuit -comprising a bistable multivibrator including two transistors each having an input and an associated output for alternately exhibiting two different voltage conditions in response to first and second input signals received at said inputs respectively when said input signals have at least a predetermined amplitude, two condensers coupled respectively to said inputs, means for charging each of said condensers, third and fourth transistors respectively coupled to said condensers, means for making said third and fourth transistors normally conductive thereby clamping the voltage across each of said condensers to a predetermined potential and preventing said charging means from being operative, two gates respectively having their outputs coupled to the inputs of said third and fourth transistors, each of the gates 'being coupled to a dilerent one of the outputs from said multivibrator transistors and being coupled in common to receive a trigger signal for gating the -trigger signal to one or the other of said third and fourth transistors in accordance with the existing voltage condition at the multivibrator transistor outputs, the leading edge of a so gated trigger signal being operative to cause the tarnsistor switch receiving same to become non-conductive thereby allowing said charging means to charge the condenser coupled to the nonconductive transistor switch, at least the trailing edge of a gating trigger signal being operative to cause the transistor switch receiving same to become conductive again thereby discharging the associated condenser and causing an input signal from the condenser, and means for limiting the amplitude to which either of the condensers may charge to said predetermined amplitude, the arrangement being such that either of said condensers may charge to said predetermined amplitude only if the trigger signal effectively causing the condenser to receive a charge exists for a time suiiciently long to allow the condenser to charge up to said predetermined amplitude.

18. A circuit as in claim 17 and further including two timing circuits for respectively coupling the ygates for their respective transistor switches and for determining the maximum time the respective transistor switches are non-conductive if the trigger signal endures longer than such time.

19. In an electronic pulse counter which includes a plurality of bistable counting circuits each having a single input terminal and at least one output terminal with the output terminals all being coupled to an AND circuit, and wherein the pulses to be counted are coupled directly to the input terminal of the lowest order countf 1l ing circuit and to the input terminals of theremaining counting circuits via other AND circuits respectively coupled to the other counting circuits and to the outputs vof each of the lower order counting circuits, the improvement wherein each of the bistable counting circuits comprises a bistable multivibrator requiring first and second input signals for respectively alternating the multivibrator between its two stableV states, means for gradually'developing and storing said rstpinput signal in resopnseto the leading edge of a trigger signal, means responsive to at least the trailing edge of said trigger signalV tor'causing the stored first input signal to be de- `livered to said multivibrator, means for gradual-1y developing and storing said second input signal in response to the leading edge of a gated trigger signal, means responsive to the trailing edge of a gated trigger signal received thereby for causing the stored input signal to bev delivered to said multivibrator, and means coupled to said trigger signal input for gating a received trigger signal to effect the rst input signal or the second input signal in accordance with the existing state of the multivibrator.

20. An Velectronic pulse counter comprising a plurality of bistable counting circuits each having an input for receiving a trigger signal and at least one output, an.

of other -AND circuits respectively coupled at their out puts to the inputs of said bistable circuits except the lowest orderV circuit for providing trigger signals thereto, each of said other AND circuits having an input from ythe `output of each lower order bistable circuit, the pulses to be counted being coupled to another input of each of said other AND circuits and directly to the trigger signal input of said lowest order counting circuit, each of said counting circuits including a multivibrator changeable between two stable states upon receipt'of successive trigger signals at least when the trigger signals have at least a predetermined amplitude, and means for each multivibrator responsive to a trigger signal `for allowing the associated multivibrator to change its state only following the occurrence ofthe trailing edge of said trigger signal.

References Cited in the file of this patent UNITED STATES PATENTS 2,883,562 Graham et al. Apr. 2l, 1959 2,885,574 Roesch May 5, 1959 2,906,894 Harris Sept. 29, 1959 v2,909,678 Jensen Oct. 20, 1959 2,912,575 Hurley Nov. l0, 1959 2,918,587 Rector et al. Dec. 22, 1959 2,923,838 Slobodzinski et al. Feb. 2, 1960 

